View HYS64T128020EDL_4122352.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

October 2007
HYS64T128020EDL-[2.5/3S/3.7]-B
2 0 0 - P i n S m a l l - O u t l i n e d D D R 2 S D R A M Mo d u l e s DDR2 SDRAM SO-DIMM SDRAM RoHS Compliant
Internet Data Sheet
Rev. 1.12
Internet Data Sheet
HYS64T128020EDL-[2.5/3S/3.7]-B Small Outlined DDR2 SDRAM Modules
HYS64T128020EDL-[2.5/3S/3.7]-B Revision History: 2007-10, Rev. 1.12 Page 6-11 All All 21 All Subjects (major changes since last revision) Editorial change and adapted to internet edition Editorial change Added Product Types HYS64T128020EDL-2.5-B and HYS64T128020EDL-3S-B Added IDD currents Qimonda update
Previous Revision: 2007-05, Rev. 1.11 Previous Revision: 2007-05, Rev. 1.1 Previous Revision: 2006-10, Rev. 1.0 Previous Revision: 2006-09, Rev. 0.51 Previous Revision: 2006-04, Rev. 0.5
We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: techdoc@qimonda.com
qag_techdoc_rev411 / 3.31 QAG / 2007-01-22 10312006-I253-V1V0
2
Internet Data Sheet
HYS64T128020EDL-[2.5/3S/3.7]-B Small Outlined DDR2 SDRAM Modules
1
Overview
This chapter gives an overview of the 200-pin small-outline DDR2 SDRAM modules product family and describes its main characteristics.
1.1
Features
* * * * * * * * * * * Auto Refresh (CBR) and Self Refresh Auto Refresh for temperatures above 85 C tREFI = 3.9 s. Programmable self refresh rate via EMRS2 setting. Programmable partial array refresh via EMRS2 settings. DCC enabling via EMRS2 setting. All inputs and outputs SSTL_1.8 compatible Off-Chip Driver Impedance Adjustment (OCD) and On-Die Termination (ODT) Serial Presence Detect with E2PROM SO-DIMM Dimensions (nominal): 50 mm42 mm30 mm high, 67.6 mm wide Based on standard reference layouts Raw Cards 'A' RoHS compliant products1)
* 200-Pin PC2-6400, PC2-5300 and PC2-4200 DDR2 SDRAM memory modules. * 128Mx64 module organization, and 64Mx16 chip organization * 1GB Modules built with 1 Gbit DDR2 SDRAMs in PGTFBGA-84-11 chipsize packages * Standard Double-Data-Rate-Two Synchronous DRAMs (DDR2 SDRAM) with a single + 1.8 V ( 0.1 V) power supply * All speed grades faster than DDR2-400 comply with DDR2-400 timing specifications. * Programmable CAS Latencies (3, 4, 5 ), Burst Length (8 & 4).
TABLE 1
Performance Table
QAG Speed Code DRAM Speed Grade Module Speed Grade CAS-RCD-RP latencies Max. Clock Frequency CL3 CL4 CL5 CL6 Min. RAS-CAS-Delay Min. Row Precharge Time Min. Row Active Time Min. Row Cycle Time DDR2 PC2 -2.5 -800E -6400E 6-6-6 -3 -667C -5300C 4-4-4 200 333 333 - 12 12 45 57 -3.7 -533C -4200C 4-4-4 200 266 266 - 15 15 45 60 Unit
tCK
MHz MHz MHz MHz ns ns ns ns
fCK3 fCK4 fCK5 fCK6 tRCD tRP tRAS tRC
200 266 333 400 15 15 45 60
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.12, 2007-10 10312006-I253-V1V0
3
Internet Data Sheet
HYS64T128020EDL-[2.5/3S/3.7]-B Small Outlined DDR2 SDRAM Modules
1.2
Description
The memory array is designed with 1 Gbit Double-Data-RateTwo (DDR2) Synchronous DRAMs. Decoupling capacitors are mounted on the PCB board. The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and are write protected; the second 128 bytes are available to the customer.
The Qimonda HYS64T128020EDL-[2.5/3S/3.7]-B module family are small-outline DIMM modules "SO-DIMMs" with 50 mm42 mm30 mm height based on DDR2 technology. DIMMs are available as non-ECC modules in128M x 64 (1GB) in organization and density, intended for mounting into 200-pin connector sockets.
TABLE 2
Ordering Information for RoHS Compliant Products
Product Type1) PC2-6400-666 HYS64T128020EDL-2.5-B 1GB 2Rx16 PC2-6400S-666-12-A0 PC2-5300-555 HYS64T128020EDL-3S-B PC2-4200-444 HYS64T128020EDL-3.7-B 1GB 2Rx16 PC2-4200S-444-12-A0 2 Ranks, Non-ECC 1Gbit (x16)
1) For detailed information regarding Product Type of Qimonda please see chapter "Product Type Nomenclature" of this datasheet. 2) The Compliance Code is printed on the module label and describes the speed grade, for example "PC2-6400S-666-12-A0" where 6400S means Small-Outline DIMM modules with 6.40 GB/sec Module Bandwidth and "666-12" means Column Address Strobe (CAS) latency =6, Row Column Delay (RCD) latency = 6 and Row Precharge (RP) latency = 6 using the latest JEDEC SPD Revision 1.2 and produced on the Raw Card "A".
Compliance Code2)
Description 2 Ranks, Non-ECC 2 Ranks, Non-ECC
SDRAM Technology 1Gbit (x16) 1Gbit (x16)
1GB 2Rx16 PC2-5300S-555-12-A0
TABLE 3
Address Format
DIMM Density 1GB Module Organization 128M x 64 Memory Ranks 2 ECC/ Non-ECC Non-ECC # of SDRAMs # of row/bank/column bits 8 13/3/10 Raw Card A
TABLE 4
Components on Modules
Product Type1)2) HYS64T128020EDL DRAM Components1) HYB18T1G160BF DRAM Density 1Gbit DRAM Organisation 64M x 16
1) Green Product 2) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet.
Rev. 1.12, 2007-10 10312006-I253-V1V0
4
Internet Data Sheet
HYS64T128020EDL-[2.5/3S/3.7]-B Small Outlined DDR2 SDRAM Modules
2
2.1
Pin Configurations and Block Diagrams
Pin Configurations
The pin configuration of the Small Outline DDR2 SDRAM DIMM is listed by function in Table 5 (200 pins). The abbreviations used in columns Pin Type and Buffer Type are explained in Table 6 and Table 7 respectively. The Pin numbering is depicted in Figure 1
TABLE 5
Pin Configuration of SO-DIMM
Pin No. Clock Signals 30 164 32 166 79 80 CK0 CK1 CK0 CK1 CKE0 CKE1 I I I I I I SSTL SSTL SSTL SSTL SSTL SSTL Clock Signals 1:0, Complement Clock Signals 1:0 The system clock inputs. All address and command lines are sampled on the cross point of the rising edge of CK and the falling edge of CK. A Delay Locked Loop (DLL) circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock. Clock Enable Rank 1:0 Activates the DDR2 SDRAM CK signal when HIGH and deactivates the CK signal when LOW. By deactivating the clocks, CKE LOW initiates the Power Down Mode or the Self Refresh Mode. Note: 2 Ranks module Not Connected Note: 1-rank module Chip Select Rank 1:0 Enables the associated DDR2 SDRAM command decoder when LOW and disables the command decoder when HIGH. When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is selected by S1. Ranks are also called "Physical banks".2 Ranks module Not Connected Note: 1-rank module Row Address Strobe When sampled at the cross point of the rising edge of CK, and falling edge of CK, RAS, CAS and WE define the operation to be executed by the SDRAM. Column Address Strobe Name Pin Type Buffer Type Function
NC Control Signals 110 115 S0 S1
NC
--
I I
SSTL SSTL
NC 108 RAS
NC I
-- SSTL
113
CAS
I
SSTL
Rev. 1.12, 2007-10 10312006-I253-V1V0
5
Internet Data Sheet
HYS64T128020EDL-[2.5/3S/3.7]-B Small Outlined DDR2 SDRAM Modules
Pin No. 109 Address Signals 107 106 85
Name WE BA0 BA1 BA2 NC
Pin Type I I I I NC I I I I I I I I I I I I I I I NC I NC
Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL -- SSTL --
Function Write Enable Bank Address Bus 2:0 Selects which DDR2 SDRAM internal bank of four or eight is activated. Bank Address Bus 2 Greater than 512Mb DDR2 SDRAMS Less than 1Gb DDR2 SDRAMS Address Bus 12:0 During a Bank Activate command cycle, defines the row address when sampled at the cross-point of the rising edge of CK and falling edge of CK. During a Read or Write command cycle, defines the column address when sampled at the cross point of the rising edge of CK and falling edge of CK. In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is HIGH, autoprecharge is selected and BA0-BAn defines the bank to be precharged. If AP is LOW, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is HIGH, all banks will be precharged regardless of the state of BA0-BAn inputs. If AP is LOW, then BA0-BAn are used to define which bank to precharge. Address Signal 12 Note: Module based on 256 Mbit or larger dies Address Signal 13 Note: 1 Gbit based module Not Connected Note: Module based on 512 Mbit or smaller dies Address Signal 14 Note: 2 Gbit based module Not Connected Note: Module based on 1 Gbit or smaller dies Data Bus 63:0 Note: Data Input / Output pins
102 101 100 99 98 97 94 92 93 91 105 90 89 116
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 AP A11 A12 A13 NC
86
A14 NC
Data Signals 5 7 17 19 4 6 14 16 23 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 I/O I/O I/O I/O I/O I/O I/O I/O I/O SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL
Rev. 1.12, 2007-10 10312006-I253-V1V0
6
Internet Data Sheet
HYS64T128020EDL-[2.5/3S/3.7]-B Small Outlined DDR2 SDRAM Modules
Pin No. 25 35 37 20 22 36 38 43 45 55 57 44 46 56 58 61 63 73 75 62 64 74 76 123 125 135 137 124 126 134 136 141 143 151 153 140 142 152 154 157
Name DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48
Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL
Function Data Bus 63:0 Note: Data Input / Output pins
Rev. 1.12, 2007-10 10312006-I253-V1V0
7
Internet Data Sheet
HYS64T128020EDL-[2.5/3S/3.7]-B Small Outlined DDR2 SDRAM Modules
Pin No. 159 173 175 158 160 174 176 179 181 189 191 180 182 192 194 Data Strobe Signals 13 11 31 29 51 49 70 68 131 129 148 146 169 167 188 186 Data Mask Signals
Name DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQS0 DQS0 DQS1 DQS1 DQS2 DQS2 DQS3 DQS3 DQS4 DQS4 DQS5 DQS5 DQS6 DQS6 DQS7 DQS7
Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL
Function Data Bus 63:0 Note: Data Input / Output pins
Data Strobe Bus 7:0 The data strobes, associated with one data byte, sourced with data transfers. In Write mode, the data strobe is sourced by the controller and is centered in the data window. In Read mode the data strobe is sourced by the DDR2 SDRAM and is sent at the leading edge of the data window. DQS signals are complements, and timing is relative to the cross-point of respective DQS and DQS. If the module is to be operated in single ended strobe mode, all DQS signals must be tied on the system board to VSS and DDR2 SDRAM mode registers programmed appropriately.
Rev. 1.12, 2007-10 10312006-I253-V1V0
8
Internet Data Sheet
HYS64T128020EDL-[2.5/3S/3.7]-B Small Outlined DDR2 SDRAM Modules
Pin No. 10 26 52 67 130 147 170 185 EEPROM 197
Name DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 SCL
Pin Type I I I I I I I I I
Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL CMOS
Function Data Mask Bus 7:0 The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is LOW but blocks the write operation if it is HIGH. In Read mode, DM lines have no effect.
Serial Bus Clock This signal is used to clock data into and out of the SPD EEPROM and Thermal sensor. Serial Bus Data This is a bidirectional pin use to transfer data into and out of the SPD EEPROM and Thermal sensor. A resistor must be connected from SDA to VDDSPD on the motherboard to act as a pull-up. Serial Address Select Bus 2:0 Address pins used to select the SPD and Thermal sensor base address. EVENT The optional EVENT pin is reserved for use to flag critical module temperature and is used in conjunction with Thermal Sensor. Not Connected Not connected on modules without temperature sensors. I/O Reference Voltage Reference voltage for the SSTL-18 inputs. EEPROM Power Supply Power supplies for Serial Presence Detect, Thermal Sensor and ground for the module. Power Supply Power supplies for core, I/O and ground for the module. Ground Plane Power supplies for core, I/O, Serial Presence Detect, Thermal Sensor and ground for the module.
195
SDA
I/O
OD
198 200 50
SA0 SA1 EVENT
I I O
CMOS CMOS OD
NC Power Supplies 1 199
-
-
VREF VDDSPD
AI PWR
-- --
81,82,87,88,95,96,103,104, 111,112,117,118
VDD
PWR GND
-- --
VSS 2,3,8,9,12,15,18,21,24,27,28, 33,34,39,40,41,42,47,48,53, 54,59,60,65,66,71,72,77,78, 121,122,127,128,132,133,138,13 9,144,145,149,150,155,156, 161,162,165,168, 171,172,177, 178,183,184,187,190,193,196
Other pins 114 ODT0
I
SSTL
On-Die Termination Control 1:0
Rev. 1.12, 2007-10 10312006-I253-V1V0
9
Internet Data Sheet
HYS64T128020EDL-[2.5/3S/3.7]-B Small Outlined DDR2 SDRAM Modules
Pin No. 119
Name ODT1
Pin Type I
Buffer Type SSTL
Function On-Die Termination Control 1 Asserts on-die termination for DQ, DM, DQS, and DQS signals if enabled via the DDR2 SDRAM mode register. Note: 2 Rank modules Not Connected Note: 1 Rank modules Not connected Pins not connected on Qimonda SO-DIMMs
NC 69,83,84,120,163 NC
NC NC
-- --
TABLE 6
Abbreviations for pin Type
Abbreviation I O I/O AI PWR GND NC Description Standard input-only pin. Digital levels. Output. Digital levels. I/O is a bidirectional input/output signal. Input. Analog levels. Power Ground Not Connected
TABLE 7
Abbreviations for Buffer Type
Abbreviation SSTL LV-CMOS CMOS OD Description Serial Stub Terminated Logic (SSTL_18) Low Voltage CMOS CMOS Levels Open Drain. The corresponding pin has 2 operational states, active low and tri-state, and allows multiple devices to share as a wire-OR.
Rev. 1.12, 2007-10 10312006-I253-V1V0
10
Internet Data Sheet
HYS64T128020EDL-[2.5/3S/3.7]-B Small Outlined DDR2 SDRAM Modules
FIGURE 1
Pin Configuration SO-DIMM (200 pin)
Rev. 1.12, 2007-10 10312006-I253-V1V0
11
Internet Data Sheet
HYS64T128020EDL-[2.5/3S/3.7]-B Small Outlined DDR2 SDRAM Modules
3
3.1
Electrical Characteristics
Absolute Maximum Ratings
Attention: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
TABLE 8
Absolute Maximum Ratings
Symbol Parameter Rating Min. Max. +2.3 +2.3 +2.3 V V V V
1) 1)1) 1)1) 1)
Unit
Note
Voltage on any pin relative to VSS -0.5 +2.3 1) When VDD and VDDQ and VDDL are less than 500 mV; VREF may be equal to or less than 300 mV.
VDD VDDQ VDDL VIN, VOUT
Voltage on VDD pin relative to VSS Voltage on VDDQ pin relative to VSS Voltage on VDDL pin relative to VSS
-1.0 -0.5 -0.5
TABLE 9
Environmental Requirements
Parameter Symbol Values Min. Operating temperature (ambient) Storage Temperature Barometric Pressure (operating & storage) Operating Humidity (relative) Storage Humidity (without condensation) Max. +65 +100 +105 90 95 C C kPa % %
1) 2)
Unit
Note
TOPR TSTG
PBar
0 - 50 +69 10 5
HOPR HSTG
1) Storage Temperature is the case surface temperature on the center/top side of the DRAM. 2) Up to 3000 m.
Rev. 1.12, 2007-10 10312006-I253-V1V0
12
Internet Data Sheet
HYS64T128020EDL-[2.5/3S/3.7]-B Small Outlined DDR2 SDRAM Modules
TABLE 10
DRAM Component Operating Temperature Range
Symbol Parameter Rating Min. Max. 95 C
1)2)3)4)
Unit
Note
TCASE
Operating Temperature
0
1) Operating Temperature is the case surface temperature on the center / top side of the DRAM. 2) The operating temperature range are the temperatures where all DRAM specification will be supported. During operation, the DRAM case temperature must be maintained between 0 - 95 C under all other specification parameters. 3) Above 85 C the Auto-Refresh command interval has to be reduced to tREFI= 3.9 s 4) When operating this product in the 85 C to 95 C TCASE temperature range, the High Temperature Self Refresh has to be enabled by setting EMR(2) bit A7 to "1". When the High Temperature Self Refresh is enabled there is an increase of IDD6 by approximately 50%
3.2
DC Operating Conditions
TABLE 11
Supply Voltage Levels and DC Operating Conditions
Parameter Symbol Values Min. Device Supply Voltage Output Supply Voltage Input Reference Voltage SPD Supply Voltage DC Input Logic High DC Input Logic Low Typ. 1.8 1.8 0.5 x VDDQ -- -- -- Max. 1.9 1.9 0.51 x VDDQ 3.6 V V V V V V
3) 1) 2)
Unit
Note
In / Output Leakage Current -5 -- 5 A 1) Under all conditions, VDDQ must be less than or equal to VDD 2) Peak to peak AC noise on VREF may not exceed 2% VREF (DC).VREF is also expected to track noise in VDDQ. 3) Input voltage for any connector pin under test of 0 V VIN VDDQ + 0.3 V; all other pins at 0 V. Current is per pin
VDD VDDQ VREF VDDSPD VIH(DC) VIL (DC) IL
1.7 1.7 0.49 x VDDQ 1.7
VREF + 0.125
- 0.30
VDDQ + 0.3 VREF - 0.125
Rev. 1.12, 2007-10 10312006-I253-V1V0
13
Internet Data Sheet
HYS64T128020EDL-[2.5/3S/3.7]-B Small Outlined DDR2 SDRAM Modules
3.3
Timing Characteristics
3.3.1
Speed Grade Definitions
TABLE 12
Speed Grade Definition
Speed Grade QAG Sort Name CAS-RCD-RP latencies Parameter Clock Period @ CL = 3 @ CL = 4 @ CL = 5 @ CL = 6 Row Active Time Row Cycle Time RAS-CAS-Delay Row Precharge Time Symbol DDR2-800E -2.5 6-6-6 Min. 5 3.75 3 2.5 45 60 15 15 Max. 8 8 8 8 70k -- -- -- Unit Note
tCK
-- ns ns ns ns ns ns ns ns
1)2)3)4) 1)2)3)4) 1)2)3)4) 1)2)3)4) 1)2)3)4)5) 1)2)3)4) 1)2)3)4) 1)2)3)4)
tCK tCK tCK tCK tRAS tRC tRCD tRP
TABLE 13
Speed Grade Definition
Speed Grade QAG Sort Name CAS-RCD-RP latencies Parameter Clock Period @ CL = 3 @ CL = 4 @ CL = 5 Row Active Time Row Cycle Time RAS-CAS-Delay Row Precharge Time Symbol DDR2-667C -3 4-4-4 Min. 5 3 3 45 57 12 12 Max. 8 8 8 70k -- -- -- DDR2-533C -3.7 4-4-4 Min. 5 3.75 3.75 45 60 15 15 Max. 8 8 8 70k -- -- -- Unit Note
tCK
-- ns ns ns ns ns ns ns
1)2)3)4) 1)2)3)4) 1)2)3)4) 1)2)3)4)5) 1)2)3)4) 1)2)3)4) 1)2)3)4)
tCK tCK tCK tRAS tRC tRCD tRP
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) mentioned in Component datasheet.
Rev. 1.12, 2007-10 10312006-I253-V1V0
14
Internet Data Sheet
HYS64T128020EDL-[2.5/3S/3.7]-B Small Outlined DDR2 SDRAM Modules
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode 3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ 4) The output timing reference voltage level is VTT. 5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI.
3.3.2
Component AC Timing Parameters
TABLE 14
DRAM Component Timing Parameter by Speed Grade - DDR2-800 and DDR2-667
Parameter Symbol DDR2-800 Min. Max. -- 0.52 8000 -- 0.52 -- DDR2-667 Min. 2 0.48 3000 3 0.48 WR + tnRP Max. -- 0.52 8000 -- 0.52 -- nCK Unit Note2)3)5
)6)7)8)
tCCD tCH.AVG Average clock period tCK.AVG CKE minimum pulse width ( high and tCKE
CAS to CAS command delay Average clock high pulse width low pulse width) Average clock low pulse width Auto-Precharge write recovery + precharge time
2 0.48 2500 3 0.48 WR + tnRP
tCK.AVG
ps nCK
10)11)
12)
tCL.AVG tDAL
tCK.AVG
nCK ns ps
10)11) 13)14)
Minimum time clocks remain ON after tDELAY CKE asynchronously drops LOW DQ and DM input hold time input
tIS + tCK .AVG -- + tIH
125 0.35 0.35 0.35 -- - 0.25 50 0.2 0.2 45 Min(tCH.ABS, tCL.ABS) -- 250 0.6 -- -- -- -- 200 + 0.25 -- -- -- -- __
tIS + -- tCK .AVG + tIH
175 0.35 0.35 0.35 -- - 0.25 100 0.2 0.2 50 Min(tCH.ABS, tCL.ABS) -- 275 0.6 -- -- -- -- 240 + 0.25 -- -- -- -- __
tDH.BASE DQ and DM input pulse width for each tDIPW tDQSH tDQSL DQS-DQ skew for DQS & associated tDQSQ
DQS input high pulse width DQS input low pulse width DQ signals DQS latching rising transition to associated clock edges DQ and DM input setup time DQS falling edge hold time from CK DQS falling edge to CK setup time Four Activate Window for 2KB page size products CK half pulse width Data-out high-impedance time from CK / CK Address and control input hold time Control & address input pulse width for each input
15)19)20)
tCK.AVG tCK.AVG tCK.AVG
ps
16)
tDQSS tDS.BASE tDSH tDSS tFAW tHP tHZ tIH.BASE tIPW
tCK.AVG
ps
17)
18)19)20) 17) 17) 35)
tCK.AVG tCK.AVG
ns ps ps ps
21)
tAC.MAX
-- --
tAC.MAX
-- --
9)22)
23)25)
tCK.AVG
Rev. 1.12, 2007-10 10312006-I253-V1V0
15
Internet Data Sheet
HYS64T128020EDL-[2.5/3S/3.7]-B Small Outlined DDR2 SDRAM Modules
Parameter
Symbol
DDR2-800 Min. Max. -- tAC.MAX
DDR2-667 Min. 200 2 x tAC.MIN Max. --
Unit
Note2)3)5
)6)7)8)
Address and control input setup time tIS.BASE DQ low impedance time from CK/CK tLZ.DQ DQS/DQS low-impedance time from CK / CK Mode register set command cycle time OCD drive mode output delay DQ/DQS output hold time from DQS DQ hold skew factor Average periodic refresh Interval Auto-Refresh to Active/Auto-Refresh command period Precharge-All (8 banks) command period Read preamble Read postamble Active to active command period for 2KB page size products
175 2 x tAC.MIN
ps ps ps ns nCK ns ps ps s s ns ns
24)25) 9)22) 9)22)
tLZ.DQS
tAC.MIN
0 2 0
tAC.MAX
12 -- 12 -- 300 7.8 3.9 --
tAC.MIN
0 2 0
tAC.MAX tAC.MAX
12 -- 12 -- 340 7.8 3.9 --
MRS command to ODT update delay tMOD
35)
tMRD tOIT tQH tQHS tREFI tRFC tRP tRPRE tRPST tRRD
35) 26) 27) 28)29) 28)30) 31)
tHP - tQHS
-- -- -- 127.5
tHP - tQHS
-- -- -- 127.5
tRP + 1 x tCK --
0.9 0.4 10 7.5 0.35 0.4 15 7.5 2 8 - AL 2 1.1 0.6 -- -- -- 0.6 -- -- -- -- --
tRP + 1 x tCK --
0.9 0.4 10 7.5 0.35 0.4 15 7.5 2 7 - AL 2 1.1 0.6 -- -- -- 0.6 -- -- -- -- --
tCK.AVG tCK.AVG
ns ns
32)33) 32)34) 35)
Internal Read to Precharge command tRTP delay
35)
tWPRE Write postamble tWPST Write recovery time tWR Internal write to read command delay tWTR Exit power down to read command tXARD Exit active power-down mode to read tXARDS
Write preamble command (slow exit, lower power) Exit precharge power-down to any valid command (other than NOP or Deselect) Exit self-refresh to a non-read command Exit self-refresh to read command Write command to DQS associated clock edges
tCK.AVG tCK.AVG
ns ns nCK nCK nCK
35) 35)36)
tXP
tXSNR tXSRD
WL
tRFC +10
200 RL - 1
-- --
tRFC +10
200 RL-1
-- --
ns nCK nCK
35)
1) For details and notes see the relevant Qimonda component data sheet 2) VDDQ = 1.8 V 0.1V; VDD = 1.8 V 0.1 V. 3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
Rev. 1.12, 2007-10 10312006-I253-V1V0
16
Internet Data Sheet
HYS64T128020EDL-[2.5/3S/3.7]-B Small Outlined DDR2 SDRAM Modules
5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode. component 6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 7) The output timing reference voltage level is VTT. component datasheet 8) New units, `tCK.AVG` and `nCK`, are introduced in DDR2-667 and DDR2-800. Unit `tCK.AVG` represents the actual tCK.AVG of the input clock under operation. Unit `nCK` represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2-400 and DDR2-533, `tCK` is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG + tERR.2PER(Min). 9) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(6-10per) of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM has tERR(6-10PER).MIN = - 272 ps and tERR(6- 10PER).MAX = + 293 ps, then tDQSCK.MIN(DERATED) = tDQSCK.MIN - tERR(6-10PER).MAX = - 400 ps - 293 ps = - 693 ps and tDQSCK.MAX(DERATED) = tDQSCK.MAX - tERR(6-10PER).MIN = 400 ps + 272 ps = + 672 ps. Similarly, tLZ.DQ for DDR2-667 derates to tLZ.DQ.MIN(DERATED) = - 900 ps - 293 ps = - 1193 ps and tLZ.DQ.MAX(DERATED) = 450 ps + 272 ps = + 722 ps. (Caution on the MIN/MAX usage!) 10) Input clock jitter spec parameter. These parameters component datasheet are referred to as 'input clock jitter spec parameters' and these parameters apply to DDR2-667 and DDR2-800 only. The jitter specified is a random jitter meeting a Gaussian distribution. 11) These parameters are specified per their average values, however it is understood that the relationship component datasheet between the average timing and the absolute instantaneous timing holds all the times (min. and max of SPEC values are to be used for calculations component datasheet). 12) tCKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + 2 x tCK + tIH. 13) DAL = WR + RU{tRP(ns) / tCK(ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For tRP, if the result of the division is not already an integer, round up to the next highest integer. tCK refers to the application clock period. Example: For DDR2-533 at tCK = 3.75 ns with tWR programmed to 4 clocks. tDAL = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks. 14) tDAL.nCK = WR [nCK] + tnRP.nCK = WR + RU{tRP [ps] / tCK.AVG[ps] }, where WR is the value programmed in the EMR. 15) Input waveform timing tDH with differential data strobe enabled MR[bit10] = 0, is referenced from the differential data strobe crosspoint to the input signal crossing at the VIH.DC level for a falling signal and from the differential data strobe crosspoint to the input signal crossing at the VIL.DC level for a rising signal applied to the device under test. DQS, DQS signals must be monotonic between VIL.DC.MAX and VIH.DC.MIN. See Figure 3. 16) tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output slew rate mismatch between DQS / DQS and associated DQ in any given cycle. 17) These parameters are measured from a data strobe signal ((L/U/R)DQS / DQS) crossing to its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC, etc.), as these are relative to the clock signal crossing. That is, these parameters should be met whether clock jitter is present or not. 18) Input waveform timing tDS with differential data strobe enabled MR[bit10] = 0, is referenced from the input signal crossing at the VIH.AC level to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL.AC level to the differential data strobe crosspoint for a falling signal applied to the device under test. DQS, DQS signals must be monotonic between Vil(DC)MAX and Vih(DC)MIN. See Figure 3. 19) If tDS or tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed. 20) These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal ((L/U/R)DQS / DQS) crossing. 21) tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not an input specification parameter. It is used in conjunction with tQHS to derive the DRAM output timing tQH. The value to be used for tQH calculation is determined by the following equation; tHP = MIN (tCH.ABS, tCL.ABS), where, tCH.ABS is the minimum of the actual instantaneous clock high time; tCL.ABS is the minimum of the actual instantaneous clock low time. 22) tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level which specifies when the device output is no longer driving (tHZ), or begins driving (tLZ) . 23) input waveform timing is referenced from the input signal crossing at the VIL.DC level for a rising signal and VIH.DC for a falling signal applied to the device under test. See Figure 4. 24) Input waveform timing is referenced from the input signal crossing at the VIH.AC level for a rising signal and VIL.AC for a falling signal applied to the device under test. See Figure 4. 25) These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC, etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should be met whether clock jitter is present or not. 26) tQH = tHP - tQHS, where: tHP is the minimum of the absolute half period of the actual input clock; and tQHS is the specification value under the max column. {The less half-pulse width distortion present, the larger the tQH value is; and the larger the valid data eye will be.} Examples: 1) If the system provides tHP of 1315 ps into a DDR2-667 SDRAM, the DRAM provides tQH of 975 ps minimum. 2) If the system provides tHP of 1420 ps into a DDR2-667 SDRAM, the DRAM provides tQH of 1080 ps minimum.
Rev. 1.12, 2007-10 10312006-I253-V1V0
17
Internet Data Sheet
HYS64T128020EDL-[2.5/3S/3.7]-B Small Outlined DDR2 SDRAM Modules
27)
28) 29) 30) 31) 32)
33)
34)
35)
36)
transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation of the output drivers. The Auto-Refresh command interval has be reduced to 3.9 s when operating the DDR2 DRAM in a temperature range between 85 C and 95 C. 0 C TCASE 85 C. 85 C < TCASE 95 C. A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device. tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (tRPST), or begins driving (tRPRE). Figure 2 shows a method to calculate these points when the device is no longer driving (tRPST), or begins driving (tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent. When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.PER of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM has tJIT.PER.MIN = - 72 ps and tJIT.PER.MAX = + 93 ps, then tRPRE.MIN(DERATED) = tRPRE.MIN + tJIT.PER.MIN = 0.9 x tCK.AVG - 72 ps = + 2178 ps and tRPRE.MAX(DERATED) = tRPRE.MAX + tJIT.PER.MAX = 1.1 x tCK.AVG + 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!). When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.DUTY of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM has tJIT.DUTY.MIN = - 72 ps and tJIT.DUTY.MAX = + 93 ps, then tRPST.MIN(DERATED) = tRPST.MIN + tJIT.DUTY.MIN = 0.4 x tCK.AVG - 72 ps = + 928 ps and tRPST.MAX(DERATED) = tRPST.MAX + tJIT.DUTY.MAX = 0.6 x tCK.AVG + 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!). For these parameters, the DDR2 SDRAM device is characterized and verified to support tnPARAM = RU{tPARAM / tCK.AVG}, which is in clock cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK.AVG}, which is in clock cycles, if all input clock jitter specifications are met. This means: For DDR2-667 5-5-5, of which tRP = 15 ns, the device will support tnRP = RU{tRP / tCK.AVG} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter. tWTR is at lease two clocks (2 x tCK) independent of operation frequency.
tQHS accounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the input is
FIGURE 2
Method for calculating transitions and endpoint
Rev. 1.12, 2007-10 10312006-I253-V1V0
18
Internet Data Sheet
HYS64T128020EDL-[2.5/3S/3.7]-B Small Outlined DDR2 SDRAM Modules
FIGURE 3
Differential input waveform timing tDS and tDH
FIGURE 4
Differential input waveform timing tlS and tlH
Rev. 1.12, 2007-10 10312006-I253-V1V0
19
Internet Data Sheet
HYS64T128020EDL-[2.5/3S/3.7]-B Small Outlined DDR2 SDRAM Modules
TABLE 15
DRAM Component Timing Parameter by Speed Grade - DDR2-533
Parameter Symbol DDR2-533 Min. CAS A to CAS B command period CK, CK high-level width CKE minimum high and low pulse width CK, CK low-level width Auto-Precharge write recovery + precharge time Minimum time clocks remain ON after CKE asynchronously drops LOW DQ and DM input hold time (differential data strobe) Max. -- 0.55 -- 0.55 -- -- -- -- -- -- -- 300 + 0.25 -- -- -- -- -- Unit Notes2)3)4)5)6)
7)
tCCD tCH tCKE tCL tDAL tDELAY tDH.BASE
2 0.45 3 0.45 WR + tRP
tCK tCK tCK tCK tCK
ns ps ps
8)
tIS + tCK + tIH
225 -25 0.35 0.35 0.35 -- - 0.25 100 -25 0.2 0.2 50 MIN. (tCL, tCH) -- 375 0.6 250 2 x tAC.MIN
9)
10)
DQ and DM input hold time (single ended tDH1.BASE data strobe) DQ and DM input pulse width (each input)
11)
tDIPW
tCK tCK tCK
ps
11)
DQS input HIGH pulse width (write cycle) tDQSH DQS input LOW pulse width (write cycle) tDQSL DQS-DQ skew (for DQS & associated DQ signals) Write command to 1st DQS latching transition
tDQSQ tDQSS
tCK
ps ps
11)
DQ and DM input setup time (differential tDS.BASE data strobe) DQ and DM input setup time (single ended data strobe) DQS falling edge hold time from CK (write cycle)
tDS1.BASE tDSH
11)
tCK tCK
ns ps ps
13) 12)
DQS falling edge to CK setup time (write tDSS cycle)
tFAW Clock half period tHP Data-out high-impedance time from CK / tHZ
Four Activate Window period CK Address and control input hold time Address and control input pulse width (each input) Address and control input setup time DQ low-impedance time from CK / CK DQS low-impedance from CK / CK MRS command to ODT update delay Mode register set command cycle time
tAC.MAX
-- -- --
13)
tIH.BASE tIPW tIS.BASE tLZ(DQ) tLZ(DQS) tMOD tMRD
11)
tCK
ps ps ps ns
11) 14) 14)
tAC.MIN
0 2
tAC.MAX tAC.MAX
12 --
tCK
Rev. 1.12, 2007-10 10312006-I253-V1V0
20
Internet Data Sheet
HYS64T128020EDL-[2.5/3S/3.7]-B Small Outlined DDR2 SDRAM Modules
Parameter
Symbol
DDR2-533 Min. Max. 12 -- 400 7.8 3.9 -- -- 1.1 0.60 -- -- -- 0.60 -- -- -- -- -- -- --
Unit
Notes2)3)4)5)6)
7)
OCD drive mode output delay Data output hold time from DQS Data hold skew factor Average periodic refresh Interval Average periodic refresh Interval Auto-Refresh to Active/Auto-Refresh command period Read preamble
tOIT tQH tQHS tREFI tREFI tRFC
0
ns ps s s ns ns
14)15) 16)18) 17)
tHP -tQHS
-- -- -- 127.5
Precharge-All (8 banks) command period tRP
tRP + 1 x tCK
0.9 0.40 10 7.5 0.25 0.40 15 7.5 2 6 - AL 2
tRPRE Read postamble tRPST Active bank A to Active bank B command tRRD
period Internal Read to Precharge command delay Write preamble Write postamble Write recovery time for write without Auto-Precharge Internal Write to Read command delay Exit power down to any valid command (other than NOP or Deselect) Exit active power-down mode to Read command (slow exit, lower power) Exit precharge power-down to any valid command (other than NOP or Deselect) Exit Self-Refresh to Read command Write recovery time for write with AutoPrecharge
tCK tCK
ns ns
14) 14) 16)22)
tRTP tWPRE tWPST tWR tWTR tXARD tXARDS tXP
tCK tCK
ns ns
19)
20) 21)
tCK tCK tCK
ns
21)
Exit Self-Refresh to non-Read command tXSNR
tRFC +10
200
tXSRD
WR
tWR/tCK
tCK tCK
22)
1) For details and notes see the relevant Qimonda component data sheet 2) VDDQ = 1.8 V 0.1V; VDD = 1.8 V 0.1 V. 3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. 5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode. component 6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 7) The output timing reference voltage level is VTT. component datasheet 8) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR parameter stored in the MR. 9) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. 10) For timing definition, refer to the Component data sheet. 11) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate mis-match between DQS / DQS and associated DQ in any given cycle.
Rev. 1.12, 2007-10 10312006-I253-V1V0
21
Internet Data Sheet
HYS64T128020EDL-[2.5/3S/3.7]-B Small Outlined DDR2 SDRAM Modules
12) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH). 13) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving (tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These parameters are verified by design and characterization, but not subject to production test. 14) The Auto-Refresh command interval has be reduced to 3.9 s when operating the DDR2 DRAM in a temperature range between 85 C and 95 C. 15) 0 C TCASE 85 C. 16) 85 C < TCASE 95 C. 17) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device 18) The tRRD timing parameter depends on the page size of the DRAM organization. 19) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 20) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies 200 z. 21) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In "standard active powerdown mode" (MR, A12 = "0") a fast power-down exit timing tXARD can be used. In "low active power-down mode" (MR, A12 ="1") a slow power-down exit timing tXARDS has to be satisfied. 22) WR must be programmed to fulfill the minimum requirement for the tWR timing parameter, where WRMIN[cycles] = tWR(ns)/tCK(ns) rounded up to the next integer value. tDAL = WR + (tRP/tCK). For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR parameter stored in the MRS.
3.3.3
ODT AC Electrical Characteristics
This chapter describes the ODT AC electrical characteristics.
TABLE 16
ODT AC Characteristics and Operating Conditions for DDR2-667 & DDR2-800
Symbol Parameter / Condition Values Min. Max. 2 Unit Note
tAOND tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD
ODT turn-on delay ODT turn-on ODT turn-on (Power-Down Modes) ODT turn-off delay ODT turn-off ODT turn-off (Power-Down Modes) ODT to Power Down Mode Entry Latency ODT Power Down Exit Latency
2
nCK
ns ns
1) 1)2) 1) 1) 1)3) 1) 1) 1)
tAC.MIN tAC.MIN + 2 ns
2.5
tAC.MAX + 0.7 ns 2 tCK + tAC.MAX + 1 ns
2.5
nCK
ns ns
tAC.MIN tAC.MIN + 2 ns
3 8
tAC.MAX + 0.6 ns 2.5 tCK + tAC.MAX + 1 ns
-- --
nCK nCK
1) New units, "tCK.AVG" and "nCK", are introduced in DDR2-667 and DDR2-800. Unit "tCK.AVG" represents the actual tCK.AVG of the input clock under operation. Unit "nCK" represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2-400 and DDR2-533, "tCK" is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG + tERR.2PER(Min). 2) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND, which is interpreted differently per speed bin. For DDR2-667/800, tAOND is 2 clock cycles after the clock edge that registered a first ODT HIGH counting the actual input clock edges. 3) ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD, which is interpreted differently per speed bin. For DDR2-667/800, if tCK(avg) = 3 ns is assumed, tAOFD is 1.5 ns (= 0.5 x 3 ns) after the second trailing clock edge counting from the clock edge that registered a first ODT LOW and by counting the actual input clock edges.
Rev. 1.12, 2007-10 10312006-I253-V1V0
22
Internet Data Sheet
HYS64T128020EDL-[2.5/3S/3.7]-B Small Outlined DDR2 SDRAM Modules
TABLE 17
ODT AC Characteristics and Operating Conditions for DDR2-533
Symbol Parameter / Condition Values Min. Max. 2 Unit Note
tAOND tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD
ODT turn-on delay ODT turn-on ODT turn-on (Power-Down Modes) ODT turn-off delay ODT turn-off ODT turn-off (Power-Down Modes) ODT to Power Down Mode Entry Latency ODT Power Down Exit Latency
2
tCK
ns ns
1)
tAC.MIN tAC.MIN + 2 ns
2.5
tAC.MAX + 1 ns 2 tCK + tAC.MAX + 1 ns
2.5
tCK
ns ns
2)
tAC.MIN tAC.MIN + 2 ns
3 8
tAC.MAX + 0.6 ns 2.5 tCK + tAC.MAX + 1 ns
-- --
tCK tCK
1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND, which is interpreted differently per speed bin. For DDR2-400/533, tAOND is 10 ns (= 2 x 5 ns) after the clock edge that registered a first ODT HIGH if tCK = 5 ns. 2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD. Both are measured from tAOFD, which is interpreted differently per speed bin. For DDR2-400/533, tAOFD is 12.5 ns (= 2.5 x 5 ns) after the clock edge that registered a first ODT HIGH if tCK = 5 ns.
Rev. 1.12, 2007-10 10312006-I253-V1V0
23
Internet Data Sheet
HYS64T128020EDL-[2.5/3S/3.7]-B Small Outlined DDR2 SDRAM Modules
3.4
IDD Specifications and Conditions
TABLE 18
IDD Measurement Conditions
List of tables defining IDD Specifications and Conditions.
Parameter
Symbol Note1)2)
3)4)5)
Operating Current 0 IDD0 One bank Active - Precharge; tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING. Operating Current 1 One bank Active - Read - Precharge; IOUT = 0 mA, BL = 4, tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, tRCD = tRCD.MIN, AL = 0, CL = CLMIN; CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING.
IDD1
6)
Precharge Standby Current IDD2N All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are SWITCHING, Databus inputs are SWITCHING. Precharge Power-Down Current Other control and address inputs are STABLE, Data bus inputs are FLOATING. Precharge Quiet Standby Current All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are STABLE, Data bus inputs are FLOATING. Active Standby Current Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN; tRAS = tRAS.MAX, tRP = tRP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA.
IDD2P IDD2Q
IDD3N
Active Power-Down Current IDD3P(0) All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit); Active Power-Down Current IDD3P(1) All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit); Operating Current - Burst Read IDD4R All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCKMIN; tRAS = tRASMAX; tRP = tRPMIN; CKE is HIGH, CS is HIGH between valid commands; Address inputs are SWITCHING; Data bus inputs are SWITCHING; IOUT = 0mA. Operating Current - Burst Write All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN; tRAS = tRAS.MAX., tRP = tRP.MAX; CKE is HIGH, CS is HIGH between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; Burst Refresh Current tCK = tCK.MIN., Refresh command every tRFC = tRFC.MIN interval, CKE is HIGH, CS is HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING. Distributed Refresh Current tCK = tCK.MIN., Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
6)
IDD4W
IDD5B
IDD5D
Rev. 1.12, 2007-10 10312006-I253-V1V0
24
Internet Data Sheet
HYS64T128020EDL-[2.5/3S/3.7]-B Small Outlined DDR2 SDRAM Modules
Parameter
Symbol Note1)2)
3)4)5)
Self-Refresh Current IDD6 CKE 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING, Data bus inputs are FLOATING. IDD6 current values are guaranteed up to TCASE of 85 C max.
6) All Bank Interleave Read Current IDD7 All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control and address bus inputs are STABLE during DESELECTS. Iout = 0 mA. 1) VDDQ = 1.8 V 0.1 V; VDD = 1.8 V 0.1 V 2) IDD specifications are tested after the device is properly initialized and IDD parameter are specified with ODT disabled. 3) Definitions for IDD see Table 19 4) For two rank modules: All active current measurements in the same IDD current mode. The other rank is in IDD2P Precharge Power-Down
Mode. 5) For details and notes see the relevant Qimonda component data sheet. 6) IDD1, IDD4R and IDD7 current measurements are defined with the outputs disabled (IOUT = 0 mA). To achieve this on module level the output buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH.
TABLE 19
Definitions for IDD
Parameter LOW STABLE FLOATING SWITCHING Description
VIN VIL(ac).MAX, HIGH is defined as VIN VIH(ac).MIN
Inputs are stable at a HIGH or LOW level Inputs are VREF = VDDQ /2 Inputs are changing between HIGH and LOW every other clock (once per 2 cycles) for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per cycle) for DQ signals not including mask or strobes.
Rev. 1.12, 2007-10 10312006-I253-V1V0
25
Internet Data Sheet
HYS64T128020EDL-[2.5/3S/3.7]-B Small Outlined DDR2 SDRAM Modules
TABLE 20
IDD Specification for HYS64T128020EDL-[2.5/3S/3.7]-B
Product Type HYS64T128020EDL-2.5-B Organization 1 GB x64 2 Ranks -2.5 HYS64T128020EDL-3S-B 1 GB x64 2 Ranks -3S 588 628 520 96 480 560 360 120 868 868 888 104 64 1248 HYS64T128020EDL-3.7-B 1 GB x64 2 Ranks -3.7 548 568 440 96 400 480 304 120 748 748 848 104 64 1168 mA mA mA mA mA mA mA mA mA mA mA mA mA mA
2) 2) 3) 3) 3) 3) 3)4) 3)5) 2) 2) 2) 3)6) 3)6) 2)
Units
Note1)
IDD0 IDD1 IDD2N IDD2P IDD2Q IDD3N IDD3P_0 (fast) IDD3P_1 (slow) IDD4R IDD4W IDD5B IDD5D IDD6 IDD7
1) 2) 3) 4) 5) 6)
648 688 560 96 520 720 384 120 1008 1008 948 104 64 1408
Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7, are defined with the outputs disabled. The other rank is in IDD2P Precharge Power-Down Current mode Both ranks are in the same IDD current mode Fast: MRS(12)=0 Slow: MRS(12)=1 IDD5D and IDD6 values are for 0C TCase 85C
Rev. 1.12, 2007-10 10312006-I253-V1V0
26
Internet Data Sheet
HYS64T128020EDL-[2.5/3S/3.7]-B Small Outlined DDR2 SDRAM Modules
4
SPD Codes
This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet. SPD stands for serial presence detect. All values with XX in the table are module specific bytes which are defined during production. List of SPD Code Tables * Table 21 "HYS64T128020EDL-2.5-B" on Page 27 * Table 22 "HYS64T128020EDL-3S-B" on Page 31 * Table 23 "HYS64T128020EDL-3.7-B" on Page 35
TABLE 21
HYS64T128020EDL-2.5-B Product Type Organization HYS64T128020EDL-2.5-B 1 GByte x64 2 Ranks (x16) Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Description Programmed SPD Bytes in EEPROM Total number of Bytes in EEPROM Memory Type (DDR2) Number of Row Addresses Number of Column Addresses DIMM Rank and Stacking Information Data Width Not used Interface Voltage Level PC2-6400S-666 Rev. 1.2 HEX 80 08 08 0D 0A 61 40 00 05 25 40 00 82 10 00 00 0C 08 70 01
tCK @ CLMAX (Byte 18) [ns] tAC SDRAM @ CLMAX (Byte 18) [ns]
Error Correction Support (non-ECC, ECC) Refresh Rate and Type Primary SDRAM Width Error Checking SDRAM Width Not used Burst Length Supported Number of Banks on SDRAM Device Supported CAS Latencies DIMM Mechanical Characteristics
Rev. 1.12, 2007-10 10312006-I253-V1V0
27
Internet Data Sheet
HYS64T128020EDL-[2.5/3S/3.7]-B Small Outlined DDR2 SDRAM Modules
Product Type Organization
HYS64T128020EDL-2.5-B 1 GByte x64 2 Ranks (x16)
Label Code JEDEC SPD Revision Byte# 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Description DIMM Type Information DIMM Attributes Component Attributes
PC2-6400S-666 Rev. 1.2 HEX 04 00 07 30 45 3D 50 3C 28 3C 2D 80 17 25 05 12 3C 1E 1E 00 06 3C 7F 80 14 1E 00 5F 58 53 3B 27 2A
tCK @ CLMAX -1 (Byte 18) [ns] tAC SDRAM @ CLMAX -1 [ns] tCK @ CLMAX -2 (Byte 18) [ns] tAC SDRAM @ CLMAX -2 [ns] tRP.MIN [ns] tRRD.MIN [ns] tRCD.MIN [ns] tRAS.MIN [ns]
Module Density per Rank
tAS.MIN and tCS.MIN [ns] tAH.MIN and tCH.MIN [ns] tDS.MIN [ns] tDH.MIN [ns] tWR.MIN [ns] tWTR.MIN [ns] tRTP.MIN [ns]
Analysis Characteristics
tRC and tRFC Extension tRC.MIN [ns] tRFC.MIN [ns] tCK.MAX [ns] tDQSQ.MAX [ns] tQHS.MAX [ns]
PLL Relock Time
TCASE.MAX Delta / T4R4W Delta
Psi(T-A) DRAM T0 (DT0) T2N (DT2N, UDIMM) or T2Q (DT2Q, RDIMM) T2P (DT2P) T3N (DT3N)
Rev. 1.12, 2007-10 10312006-I253-V1V0
28
Internet Data Sheet
HYS64T128020EDL-[2.5/3S/3.7]-B Small Outlined DDR2 SDRAM Modules
Product Type Organization
HYS64T128020EDL-2.5-B 1 GByte x64 2 Ranks (x16)
Label Code JEDEC SPD Revision Byte# 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 Description T3P.fast (DT3P fast) T3P.slow (DT3P slow) T4R (DT4R) / T4R4W Sign (DT4R4W) T5B (DT5B) T7 (DT7) Psi(ca) PLL Psi(ca) REG TPLL (DTPLL) TREG (DTREG) / Toggle Rate SPD Revision Checksum of Bytes 0-62 Manufacturer's JEDEC ID Code (1) Manufacturer's JEDEC ID Code (2) Manufacturer's JEDEC ID Code (3) Manufacturer's JEDEC ID Code (4) Manufacturer's JEDEC ID Code (5) Manufacturer's JEDEC ID Code (6) Manufacturer's JEDEC ID Code (7) Manufacturer's JEDEC ID Code (8) Module Manufacturer Location Product Type, Char 1 Product Type, Char 2 Product Type, Char 3 Product Type, Char 4 Product Type, Char 5 Product Type, Char 6 Product Type, Char 7 Product Type, Char 8 Product Type, Char 9 Product Type, Char 10 Product Type, Char 11 Product Type, Char 12 Product Type, Char 13
PC2-6400S-666 Rev. 1.2 HEX 43 1E 54 22 42 00 00 00 00 12 22 7F 7F 7F 7F 7F 51 00 00 xx 36 34 54 31 32 38 30 32 30 45 44 4C 32
Rev. 1.12, 2007-10 10312006-I253-V1V0
29
Internet Data Sheet
HYS64T128020EDL-[2.5/3S/3.7]-B Small Outlined DDR2 SDRAM Modules
Product Type Organization
HYS64T128020EDL-2.5-B 1 GByte x64 2 Ranks (x16)
Label Code JEDEC SPD Revision Byte# 86 87 88 89 90 91 92 93 94 95 - 98 128 255 Description Product Type, Char 14 Product Type, Char 15 Product Type, Char 16 Product Type, Char 17 Product Type, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number Blank for customer use
PC2-6400S-666 Rev. 1.2 HEX 2E 35 42 20 20 0x xx xx xx xx 00 FF
99 - 127 Not used
Rev. 1.12, 2007-10 10312006-I253-V1V0
30
Internet Data Sheet
HYS64T128020EDL-[2.5/3S/3.7]-B Small Outlined DDR2 SDRAM Modules
TABLE 22
HYS64T128020EDL-3S-B Product Type Organization HYS64T128020EDL-3S-B 1 GByte x64 2 Ranks (x16) Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Description Programmed SPD Bytes in EEPROM Total number of Bytes in EEPROM Memory Type (DDR2) Number of Row Addresses Number of Column Addresses DIMM Rank and Stacking Information Data Width Not used Interface Voltage Level PC2-5300S-555 Rev. 1.2 HEX 80 08 08 0D 0A 61 40 00 05 30 45 00 82 10 00 00 0C 08 38 01 04 00 07 3D 50 50 60 3C 28 3C
tCK @ CLMAX (Byte 18) [ns] tAC SDRAM @ CLMAX (Byte 18) [ns]
Error Correction Support (non-ECC, ECC) Refresh Rate and Type Primary SDRAM Width Error Checking SDRAM Width Not used Burst Length Supported Number of Banks on SDRAM Device Supported CAS Latencies DIMM Mechanical Characteristics DIMM Type Information DIMM Attributes Component Attributes
tCK @ CLMAX -1 (Byte 18) [ns] tAC SDRAM @ CLMAX -1 [ns] tCK @ CLMAX -2 (Byte 18) [ns] tAC SDRAM @ CLMAX -2 [ns] tRP.MIN [ns] tRRD.MIN [ns] tRCD.MIN [ns]
Rev. 1.12, 2007-10 10312006-I253-V1V0
31
Internet Data Sheet
HYS64T128020EDL-[2.5/3S/3.7]-B Small Outlined DDR2 SDRAM Modules
Product Type Organization
HYS64T128020EDL-3S-B 1 GByte x64 2 Ranks (x16)
Label Code JEDEC SPD Revision Byte# 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 Description
PC2-5300S-555 Rev. 1.2 HEX 2D 80 20 27 10 17 3C 1E 1E 00 06 3C 7F 80 18 22 00 5D 58 43 32 27 24 39 1E 48 21 34 00 00 00 00 12
tRAS.MIN [ns]
Module Density per Rank
tAS.MIN and tCS.MIN [ns] tAH.MIN and tCH.MIN [ns] tDS.MIN [ns] tDH.MIN [ns] tWR.MIN [ns] tWTR.MIN [ns] tRTP.MIN [ns]
Analysis Characteristics
tRC and tRFC Extension tRC.MIN [ns] tRFC.MIN [ns] tCK.MAX [ns] tDQSQ.MAX [ns] tQHS.MAX [ns]
PLL Relock Time
TCASE.MAX Delta / T4R4W Delta
Psi(T-A) DRAM T0 (DT0) T2N (DT2N, UDIMM) or T2Q (DT2Q, RDIMM) T2P (DT2P) T3N (DT3N) T3P.fast (DT3P fast) T3P.slow (DT3P slow) T4R (DT4R) / T4R4W Sign (DT4R4W) T5B (DT5B) T7 (DT7) Psi(ca) PLL Psi(ca) REG TPLL (DTPLL) TREG (DTREG) / Toggle Rate SPD Revision
Rev. 1.12, 2007-10 10312006-I253-V1V0
32
Internet Data Sheet
HYS64T128020EDL-[2.5/3S/3.7]-B Small Outlined DDR2 SDRAM Modules
Product Type Organization
HYS64T128020EDL-3S-B 1 GByte x64 2 Ranks (x16)
Label Code JEDEC SPD Revision Byte# 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 - 98 Description Checksum of Bytes 0-62 Manufacturer's JEDEC ID Code (1) Manufacturer's JEDEC ID Code (2) Manufacturer's JEDEC ID Code (3) Manufacturer's JEDEC ID Code (4) Manufacturer's JEDEC ID Code (5) Manufacturer's JEDEC ID Code (6) Manufacturer's JEDEC ID Code (7) Manufacturer's JEDEC ID Code (8) Module Manufacturer Location Product Type, Char 1 Product Type, Char 2 Product Type, Char 3 Product Type, Char 4 Product Type, Char 5 Product Type, Char 6 Product Type, Char 7 Product Type, Char 8 Product Type, Char 9 Product Type, Char 10 Product Type, Char 11 Product Type, Char 12 Product Type, Char 13 Product Type, Char 14 Product Type, Char 15 Product Type, Char 16 Product Type, Char 17 Product Type, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number
PC2-5300S-555 Rev. 1.2 HEX 12 7F 7F 7F 7F 7F 51 00 00 xx 36 34 54 31 32 38 30 32 30 45 44 4C 33 53 42 20 20 20 1x xx xx xx xx
Rev. 1.12, 2007-10 10312006-I253-V1V0
33
Internet Data Sheet
HYS64T128020EDL-[2.5/3S/3.7]-B Small Outlined DDR2 SDRAM Modules
Product Type Organization
HYS64T128020EDL-3S-B 1 GByte x64 2 Ranks (x16)
Label Code JEDEC SPD Revision Byte# 128 255 Description Blank for customer use
PC2-5300S-555 Rev. 1.2 HEX 00 FF
99 - 127 Not used
Rev. 1.12, 2007-10 10312006-I253-V1V0
34
Internet Data Sheet
HYS64T128020EDL-[2.5/3S/3.7]-B Small Outlined DDR2 SDRAM Modules
TABLE 23
HYS64T128020EDL-3.7-B Product Type Organization HYS64T128020EDL-3.7-B 1 GByte x64 2 Ranks (x16) Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Description Programmed SPD Bytes in EEPROM Total number of Bytes in EEPROM Memory Type (DDR2) Number of Row Addresses Number of Column Addresses DIMM Rank and Stacking Information Data Width Not used Interface Voltage Level PC2-4200S-444 Rev. 1.2 HEX 80 08 08 0D 0A 61 40 00 05 3D 50 00 82 10 00 00 0C 08 38 00 04 00 07 3D 50 50 60 3C 28 3C
tCK @ CLMAX (Byte 18) [ns] tAC SDRAM @ CLMAX (Byte 18) [ns]
Error Correction Support (non-ECC, ECC) Refresh Rate and Type Primary SDRAM Width Error Checking SDRAM Width Not used Burst Length Supported Number of Banks on SDRAM Device Supported CAS Latencies DIMM Mechanical Characteristics DIMM Type Information DIMM Attributes Component Attributes
tCK @ CLMAX -1 (Byte 18) [ns] tAC SDRAM @ CLMAX -1 [ns] tCK @ CLMAX -2 (Byte 18) [ns] tAC SDRAM @ CLMAX -2 [ns] tRP.MIN [ns] tRRD.MIN [ns] tRCD.MIN [ns]
Rev. 1.12, 2007-10 10312006-I253-V1V0
35
Internet Data Sheet
HYS64T128020EDL-[2.5/3S/3.7]-B Small Outlined DDR2 SDRAM Modules
Product Type Organization
HYS64T128020EDL-3.7-B 1 GByte x64 2 Ranks (x16)
Label Code JEDEC SPD Revision Byte# 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 Description
PC2-4200S-444 Rev. 1.2 HEX 2D 80 25 37 10 22 3C 1E 1E 00 06 3C 7F 80 1E 28 00 59 60 3F 2A 2B 20 35 21 40 22 31 00 00 00 00 12
tRAS.MIN [ns]
Module Density per Rank
tAS.MIN and tCS.MIN [ns] tAH.MIN and tCH.MIN [ns] tDS.MIN [ns] tDH.MIN [ns] tWR.MIN [ns] tWTR.MIN [ns] tRTP.MIN [ns]
Analysis Characteristics
tRC and tRFC Extension tRC.MIN [ns] tRFC.MIN [ns] tCK.MAX [ns] tDQSQ.MAX [ns] tQHS.MAX [ns]
PLL Relock Time
TCASE.MAX Delta / T4R4W Delta
Psi(T-A) DRAM T0 (DT0) T2N (DT2N, UDIMM) or T2Q (DT2Q, RDIMM) T2P (DT2P) T3N (DT3N) T3P.fast (DT3P fast) T3P.slow (DT3P slow) T4R (DT4R) / T4R4W Sign (DT4R4W) T5B (DT5B) T7 (DT7) Psi(ca) PLL Psi(ca) REG TPLL (DTPLL) TREG (DTREG) / Toggle Rate SPD Revision
Rev. 1.12, 2007-10 10312006-I253-V1V0
36
Internet Data Sheet
HYS64T128020EDL-[2.5/3S/3.7]-B Small Outlined DDR2 SDRAM Modules
Product Type Organization
HYS64T128020EDL-3.7-B 1 GByte x64 2 Ranks (x16)
Label Code JEDEC SPD Revision Byte# 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 - 98 Description Checksum of Bytes 0-62 Manufacturer's JEDEC ID Code (1) Manufacturer's JEDEC ID Code (2) Manufacturer's JEDEC ID Code (3) Manufacturer's JEDEC ID Code (4) Manufacturer's JEDEC ID Code (5) Manufacturer's JEDEC ID Code (6) Manufacturer's JEDEC ID Code (7) Manufacturer's JEDEC ID Code (8) Module Manufacturer Location Product Type, Char 1 Product Type, Char 2 Product Type, Char 3 Product Type, Char 4 Product Type, Char 5 Product Type, Char 6 Product Type, Char 7 Product Type, Char 8 Product Type, Char 9 Product Type, Char 10 Product Type, Char 11 Product Type, Char 12 Product Type, Char 13 Product Type, Char 14 Product Type, Char 15 Product Type, Char 16 Product Type, Char 17 Product Type, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number
PC2-4200S-444 Rev. 1.2 HEX 42 7F 7F 7F 7F 7F 51 00 00 xx 36 34 54 31 32 38 30 32 30 45 44 4C 33 2E 37 42 20 20 3x xx xx xx xx
Rev. 1.12, 2007-10 10312006-I253-V1V0
37
Internet Data Sheet
HYS64T128020EDL-[2.5/3S/3.7]-B Small Outlined DDR2 SDRAM Modules
Product Type Organization
HYS64T128020EDL-3.7-B 1 GByte x64 2 Ranks (x16)
Label Code JEDEC SPD Revision Byte# 128 255 Description Blank for customer use
PC2-4200S-444 Rev. 1.2 HEX 00 FF
99 - 127 Not used
Rev. 1.12, 2007-10 10312006-I253-V1V0
38
Internet Data Sheet
HYS64T128020EDL-[2.5/3S/3.7]-B Small Outlined DDR2 SDRAM Modules
5
Package Outlines
FIGURE 5
Package Outline Raw Card A L-DIM-200-31
Notes 1. Thermal Sensor (Optional) 2. SPD or Combidevice (if used then no Thermal Sensor needed)
Rev. 1.12, 2007-10 10312006-I253-V1V0
39
Internet Data Sheet
HYS64T128020EDL-[2.5/3S/3.7]-B Small Outlined DDR2 SDRAM Modules
6
Product Type Nomenclature
field number. The detailed field description together with possible values and coding explanation is listed for modules in Table 25 and for components in Table 26.
Qimonda's nomenclature uses simple coding combined with some proprietary coding. Table 24 provides examples for module and component product type number as well as the
TABLE 24
Nomenclature Fields and Examples
Example for Field Number 1 Micro-DIMM DDR2 DRAM HYS HYB 2 64 18 3 T T 4 64/128 5 0 6 2 7 0 0 8 K A 9 M C 10 -5 -5 11 -A
512/1G 16
TABLE 25
DDR2 DIMM Nomenclature
Field 1 2 3 4 Description Qimonda Module Prefix Module Data Width [bit] DRAM Technology Memory Density per I/O [Mbit]; Module Density1) Values HYS 64 72 T 32 64 128 256 512 5 6 7 8 9 Raw Card Generation Number of Module Ranks Product Variations Package, Lead-Free Status Module Type 0 .. 9 0, 2, 4 0 .. 9 A .. Z D M R U F Coding Constant Non-ECC ECC DDR2 256 MByte 512 MByte 1 GByte 2 GByte 4 GByte Look up table 1, 2, 4 Look up table Look up table SO-DIMM Micro-DIMM Registered Unbuffered Fully Buffered
Rev. 1.12, 2007-10 10312006-I253-V1V0
40
Internet Data Sheet
HYS64T128020EDL-[2.5/3S/3.7]-B Small Outlined DDR2 SDRAM Modules
Field 10
Description Speed Grade
Values -19F -1.9 -25F -2.5 -3 -3S -3.7 -5
Coding PC2-8500 6-6-6 PC2-8500 7-7-7 PC2-6400 5-5-5 PC2-6400 6-6-6 PC2-5300 4-4-4 PC2-5300 5-5-5 PC2-4200 4-4-4 PC2-3200 3-3-3 First Second
11
Die Revision
-A -B
1) Multiplying "Memory Density per I/O" with "Module Data Width" and dividing by 8 for Non-ECC and 9 for ECC modules gives the overall module memory density in MBytes as listed in column "Coding".
TABLE 26
DDR2 DRAM Nomenclature
Field 1 2 3 4 Description Qimonda Component Prefix Interface Voltage [V] DRAM Technology Component Density [Mbit] Values HYB 18 T 256 512 1G 2G 5+6 Number of I/Os 40 80 16 7 8 9 10 Product Variations Die Revision Package, Lead-Free Status Speed Grade 0 .. 9 A B C F -19F -1.9 -25F -2.5 -3 -3S -3.7 -5 Coding Constant SSTL_18 DDR2 256 Mbit 512 Mbit 1 Gbit 2 Gbit x4 x8 x16 Look up table First Second FBGA, lead-containing FBGA, lead-free PC2-8500 6-6-6 PC2-8500 7-7-7 PC2-6400 5-5-5 PC2-6400 6-6-6 PC2-5300 4-4-4 PC2-5300 5-5-5 PC2-4200 4-4-4 PC2-3200 3-3-3
Rev. 1.12, 2007-10 10312006-I253-V1V0
41
Internet Data Sheet
HYS64T128020EDL-[2.5/3S/3.7]-B Small Outlined DDR2 SDRAM Modules
Contents
1 1.1 1.2 2 2.1 3 3.1 3.2 3.3 3.3.1 3.3.2 3.3.3 3.4 4 5 6 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin Configurations and Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Speed Grade Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Component AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ODT AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDD Specifications and Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 12 13 14 14 15 22 24
SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Product Type Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Rev. 1.12, 2007-10 10312006-I253-V1V0
42
Internet Data Sheet
Edition 2007-10 Published by Qimonda AG Gustav-Heinemann-Ring 212 D-81739 Munchen, Germany (c) Qimonda AG 2007. All Rights Reserved. Legal Disclaimer The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Qimonda Office. Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. www.qimonda.com

▲Up To Search▲

Price & Availability of HYS64T128020EDL

	To Download HYS64T128020EDL Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .